33 lines
748 B
Coq
33 lines
748 B
Coq
|
/*
|
||
|
|
Stack
|
||
|
|
*/
|
||
|
|
|
||
|
|
module stack #(
|
||
|
|
parameter DEPTH = 256,
|
||
|
|
parameter W = 16
|
||
|
|
) (
|
||
|
|
input clk,
|
||
|
|
input rst,
|
||
|
|
input push,
|
||
|
|
input pop,
|
||
|
|
input [W-1:0] value,
|
||
|
|
output reg [W-1:0] out
|
||
|
|
);
|
||
|
|
reg [W-1:0] mem [0:DEPTH-1];
|
||
|
|
reg [$clog2(DEPTH):0] sp; // bit extra para detectar overflow
|
||
|
|
|
||
|
|
wire full = (sp == DEPTH);
|
||
|
|
wire empty = (sp == 0);
|
||
|
|
|
||
|
|
always @(posedge clk or posedge rst) begin
|
||
|
|
if (rst) begin
|
||
|
|
sp <= 0;
|
||
|
|
end else if (push && !full) begin
|
||
|
|
mem[sp] <= value;
|
||
|
|
sp <= sp + 1;
|
||
|
|
end else if (pop && !empty) begin
|
||
|
|
out <= mem[sp - 1];
|
||
|
|
sp <= sp - 1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
endmodule
|