48 lines
1.3 KiB
Coq
48 lines
1.3 KiB
Coq
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`include "./shift_register/shift_register.v"
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module shift_register_tb;
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reg clk, rst, load, shift_en, dir, serial_in;
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reg [7:0] parallel_in;
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wire [7:0] q;
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wire serial_out;
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shift_register register(
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.clk(clk),
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.rst(rst),
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.load(load),
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.shift_en(shift_en),
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.dir(dir),
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.serial_in(serial_in),
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.parallel_in(parallel_in),
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.q(q),
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.serial_out(serial_out)
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);
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initial clk = 0;
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always #5 clk = ~clk;
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initial begin
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$dumpfile("./shift_register/shift_register.vcd");
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$dumpvars(0, shift_register_tb);
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rst = 1; load = 0; shift_en = 1; dir = 0; serial_in = 0;
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@(posedge clk);
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$display("rst=%b, load=%b, shift_en=%b, dir=%b, serial_in=%b, q=%b", rst, load, shift_en, dir, serial_in, q);
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rst = 0; load = 1; parallel_in = 64;
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@(posedge clk);
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$display("rst=%b, load=%b, shift_en=%b, dir=%b, serial_in=%b, q=%b", rst, load, shift_en, dir, serial_in, q);
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load = 0; serial_in = 1;
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@(posedge clk);
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$display("rst=%b, load=%b, shift_en=%b, dir=%b, serial_in=%b, q=%b", rst, load, shift_en, dir, serial_in, q);
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repeat(10) @(posedge clk);
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$display("rst=%b, load=%b, shift_en=%b, dir=%b, serial_in=%b, q=%b", rst, load, shift_en, dir, serial_in, q);
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$finish;
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end
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endmodule
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