add rom

roadmap.md

@@ -352,7 +352,7 @@ gtkwave modulo.vcd
 - [x] Fase 2.3 — Shift Register
 - [x] Fase 2.4 — Register File
 - [x] Fase 3.1 — RAM sincrona
-- [ ] Fase 3.2 — ROM
+- [x] Fase 3.2 — ROM
 - [ ] Fase 3.3 — Stack
 - [ ] Fase 4.1 — FSM Semaforo
 - [ ] Fase 4.2 — UART TX

rom/program.hex

@@ -0,0 +1,5 @@
+BEEF
+1234
+ABCD
+0000
+FF00

rom/rom.v

@@ -0,0 +1,21 @@
+/*
+    ROM
+*/
+
+module rom #(
+    parameter DEPTH = 256,
+    parameter W     = 16,
+    parameter FILE  = ""
+) (
+    input                       clk,
+    input [$clog2(DEPTH)-1:0]   addr,
+    output reg [W-1:0]          rd_data
+);
+    reg [W-1:0] mem [0:DEPTH-1];
+
+    initial $readmemh(FILE, mem);
+
+    always @(posedge clk) begin
+        rd_data <= mem[addr];        
+    end
+endmodule

rom/rom_tb.v

@@ -0,0 +1,44 @@
+/*
+    ROM
+*/
+`include "rom/rom.v"
+
+module rom_tb;
+    reg clk;
+    reg [7:0]   addr;
+    wire [15:0] rd_data;
+
+    rom #(.FILE("rom/program.hex")) rom1(
+        .clk(clk),
+        .addr(addr),
+        .rd_data(rd_data)
+    );
+
+    initial clk = 0;
+    always #5 clk = ~clk;
+
+    initial begin
+        $dumpfile("rom/rom.vcd");
+        $dumpvars(0, rom_tb);
+
+        addr = 0;
+        @(posedge clk);
+        $display("addr=%d, rd_data=%x", addr, rd_data);
+        @(posedge clk);
+        $display("addr=%d, rd_data=%x", addr, rd_data);
+
+        addr = 1;
+        @(posedge clk);
+        $display("addr=%d, rd_data=%x", addr, rd_data);
+        @(posedge clk);
+        $display("addr=%d, rd_data=%x", addr, rd_data);
+
+        addr = 2;
+        @(posedge clk);
+        $display("addr=%d, rd_data=%x", addr, rd_data);
+        @(posedge clk);
+        $display("addr=%d, rd_data=%x", addr, rd_data);
+        
+        $finish;
+    end
+endmodule