44 lines
938 B
Verilog
44 lines
938 B
Verilog
/*
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ROM
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*/
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`include "rom/rom.v"
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module rom_tb;
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reg clk;
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reg [7:0] addr;
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wire [15:0] rd_data;
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rom #(.FILE("rom/program.hex")) rom1(
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.clk(clk),
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.addr(addr),
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.rd_data(rd_data)
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);
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initial clk = 0;
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always #5 clk = ~clk;
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initial begin
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$dumpfile("rom/rom.vcd");
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$dumpvars(0, rom_tb);
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addr = 0;
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@(posedge clk);
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$display("addr=%d, rd_data=%x", addr, rd_data);
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@(posedge clk);
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$display("addr=%d, rd_data=%x", addr, rd_data);
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addr = 1;
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@(posedge clk);
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$display("addr=%d, rd_data=%x", addr, rd_data);
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@(posedge clk);
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$display("addr=%d, rd_data=%x", addr, rd_data);
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addr = 2;
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@(posedge clk);
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$display("addr=%d, rd_data=%x", addr, rd_data);
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@(posedge clk);
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$display("addr=%d, rd_data=%x", addr, rd_data);
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$finish;
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end
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endmodule |