add shift_register

shift_register/shift_register.v

@@ -0,0 +1,24 @@
+module shift_register #(parameter N = 8) (
+    input clk,
+    input rst,
+    input load,
+    input shift_en,
+    input dir,
+    input serial_in,
+    input [N-1:0] parallel_in,
+    output reg [N-1:0] q,
+    output serial_out
+);
+
+    assign serial_out = dir ? q[0] : q[N-1];
+
+    always @(posedge clk or posedge rst) begin
+        if (rst) q <= 0;
+        else if (load) q <= parallel_in;
+        else if (shift_en) begin
+            if (dir == 0) q <= {q[N-2:0], serial_in};
+            else q <= {serial_in, q[N-1:1]};
+        end
+    end
+
+endmodule