add ram

ram/ram_tb.v

@@ -0,0 +1,54 @@
+/*
+    Ram Sincrona testbench
+*/
+`include "ram/ram.v"
+
+module ram_tb;
+    reg clk, wr_en;
+    reg [7:0]   addr;
+    reg [15:0]  wr_data;
+    wire [15:0] rd_data;
+
+    ram ram1(
+        .clk(clk),
+        .wr_en(wr_en),
+        .addr(addr),
+        .wr_data(wr_data),
+        .rd_data(rd_data)
+    );
+
+    initial clk = 0;
+    always #5 clk = ~clk;
+
+    initial begin
+        $dumpfile("ram/ram.vcd");
+        $dumpvars(0, ram_tb);
+
+        wr_en = 0; addr = 0; wr_data = 0;
+        @(posedge clk);
+        $display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
+
+        wr_en = 1; addr = 25; wr_data = 256;
+        @(posedge clk);
+        $display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
+
+        wr_en = 0;
+        @(posedge clk);
+        $display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
+
+        @(posedge clk);
+        $display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
+
+        addr = 16;
+
+        @(posedge clk);
+        $display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
+
+        @(posedge clk);
+        $display("wr_en=%b, addr=%d, wr_data=%d, rd_data=%d", wr_en, addr, wr_data, rd_data);
+
+
+        $finish;
+    end
+    
+endmodule