add fsm_traffic

fsm_traffic/fsm_traffic.v

@@ -0,0 +1,48 @@
+/*
+    fsm_traffic
+*/
+module fsm_traffic (
+    input clk,
+    input rst,
+    output red_led,
+    output green_led,
+    output yellow_led
+);
+    localparam RED      = 2'b00;
+    localparam GREEN    = 2'b01;
+    localparam YELLOW   = 2'b10;
+
+    reg[1:0] state, next_state;
+    reg[7:0] timer;
+
+    always @(posedge clk or posedge rst) begin
+       if (rst) begin
+        state <= RED;
+        timer <= 3;
+       end
+       else if (timer == 0) begin
+            state <= next_state;
+
+            case (next_state)
+                RED:     timer <= 3;
+                YELLOW:  timer <= 1;
+                GREEN:   timer <= 2;
+                default: timer <= 3;
+            endcase
+       end
+       else timer <= timer - 1; 
+    end
+
+    always @(*) begin
+        case (state)
+            RED:     next_state = GREEN;
+            YELLOW:  next_state = RED;
+            GREEN:   next_state = YELLOW;
+            default: next_state = RED;
+        endcase
+    end
+
+    assign red_led = state == RED;
+    assign green_led = state == GREEN;
+    assign yellow_led = state == YELLOW;
+endmodule

fsm_traffic/fsm_traffic_tb.v

@@ -0,0 +1,56 @@
+/*
+    fsm_traffic testbench
+*/
+`include "fsm_traffic/fsm_traffic.v"
+
+module fsm_traffic_tb;
+    reg clk, rst;
+    wire red_led, green_led, yellow_led;
+
+    fsm_traffic dut (
+        .clk(clk),
+        .rst(rst),
+        .red_led(red_led),
+        .green_led(green_led),
+        .yellow_led(yellow_led)
+    );
+
+    initial clk = 0;
+    always #5 clk = ~clk;
+
+    task show_state;
+        $display("t=%0t | rst=%b | R=%b G=%b Y=%b",
+            $time, rst, red_led, green_led, yellow_led);
+    endtask
+
+    initial begin
+        $dumpfile("fsm_traffic/fsm_traffic.vcd");
+        $dumpvars(0, fsm_traffic_tb);
+
+        // Reset
+        rst = 1;
+        @(posedge clk); #1
+        show_state;
+
+        rst = 0;
+
+        // Dejar correr varios ciclos para ver todos los estados
+        repeat(9) begin
+            @(posedge clk); #1
+            show_state;
+        end
+
+        // Reset a mitad de secuencia — debe volver a RED
+        rst = 1;
+        @(posedge clk); #1
+        show_state;
+        rst = 0;
+
+        repeat(3) begin
+            @(posedge clk); #1
+            show_state;
+        end
+
+        $finish;
+    end
+endmodule

roadmap.md

@@ -353,8 +353,8 @@ gtkwave modulo.vcd
 - [x] Fase 2.4 — Register File
 - [x] Fase 3.1 — RAM sincrona
 - [x] Fase 3.2 — ROM
-- [ ] Fase 3.3 — Stack
-- [ ] Fase 4.1 — FSM Semaforo
+- [x] Fase 3.3 — Stack
+- [x] Fase 4.1 — FSM Semaforo
 - [ ] Fase 4.2 — UART TX
 - [ ] Fase 5.1 — Fetch Unit
 - [ ] Fase 5.2 — Decoder de instrucciones

stack/stack.v

@@ -0,0 +1,33 @@
+/*
+    Stack
+*/
+
+module stack #(
+    parameter DEPTH = 256,
+    parameter W     = 16
+) (
+    input               clk,
+    input               rst,
+    input               push,
+    input               pop,
+    input [W-1:0]       value,
+    output reg [W-1:0]  out
+);
+    reg [W-1:0] mem [0:DEPTH-1];
+    reg [$clog2(DEPTH):0] sp;  // bit extra para detectar overflow
+
+    wire full  = (sp == DEPTH);
+    wire empty = (sp == 0);
+
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            sp <= 0;
+        end else if (push && !full) begin
+            mem[sp] <= value;
+            sp <= sp + 1;
+        end else if (pop && !empty) begin
+            out <= mem[sp - 1];
+            sp <= sp - 1;
+        end
+    end
+endmodule

stack/stack_tb.v

@@ -0,0 +1,63 @@
+/*
+    Stack testbench
+*/
+
+`include "stack/stack.v"
+
+module stack_tb;
+    reg clk, rst, push, pop;
+    reg[15:0]   in;
+    wire [15:0] out;
+
+    stack stack1(
+        .clk(clk),
+        .rst(rst),
+        .push(push),
+        .pop(pop),
+        .value(in),
+        .out(out)
+    );
+
+    initial clk = 0;
+    always #5 clk = ~clk;
+
+    initial begin
+        $dumpfile("stack/stack.vcd");
+        $dumpvars(0, stack_tb);
+
+        rst = 1; push = 0; pop = 0; in = 0;
+        @(posedge clk); #1
+        rst = 0;
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+
+        push = 1; pop = 0; in = 69;
+        @(posedge clk); #1
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+
+        push = 1; pop = 0; in = 40;
+        @(posedge clk); #1
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+
+        push = 0; pop = 0; in = 0;
+        @(posedge clk); #1
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+
+        push = 0; pop = 1; in = 0;
+        @(posedge clk); #1
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+        push = 0; pop = 0; in = 0;
+        @(posedge clk); #1
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+
+
+        push = 0; pop = 1; in = 0;
+        @(posedge clk); #1 
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+        push = 0; pop = 0; in = 0;
+        @(posedge clk); #1
+        $display("push=%b, pop=%b, value=%x, out=%x", push, pop, in, out);
+
+
+        $finish;
+    end
+endmodule