43 lines
1.1 KiB
Verilog
43 lines
1.1 KiB
Verilog
`include "./mux_demux/mux_demux.v"
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module mux_demux_tb();
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reg [7:0] a, b;
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reg sel;
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wire [7:0] out, _a, _b;
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mux_Nn1 #(.DATA_W(8), .SEL_W(1)) mux (
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.in({b, a}),
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.sel(sel),
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.out(out)
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);
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demux_1n2 demux (
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.in(out),
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.sel(sel),
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.a(_a),
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.b(_b)
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);
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initial begin
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$dumpfile("./mux_demux/mux_demux.vcd");
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$dumpvars(0, mux_demux_tb);
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a = 20; b = 5; sel = 0;
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#1
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$display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
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a = 21; b = 5; sel = 0;
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#1
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$display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
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a = 22; b = 5; sel = 0;
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#1
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$display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
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a = 22; b = 5; sel = 1;
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#1
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$display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
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a = 22; b = 15; sel = 1;
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#1
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$display("a=%d, b=%d, sel=%b out=%d _a=%d, _b=%d", a, b, sel, out, _a, _b);
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end
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endmodule |