21 lines
385 B
Verilog
21 lines
385 B
Verilog
/*
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ROM
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*/
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module rom #(
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parameter DEPTH = 256,
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parameter W = 16,
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parameter FILE = ""
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) (
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input clk,
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input [$clog2(DEPTH)-1:0] addr,
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output reg [W-1:0] rd_data
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);
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reg [W-1:0] mem [0:DEPTH-1];
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initial $readmemh(FILE, mem);
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always @(posedge clk) begin
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rd_data <= mem[addr];
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end
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endmodule |