24 lines
549 B
Verilog
24 lines
549 B
Verilog
module shift_register #(parameter N = 8) (
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input clk,
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input rst,
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input load,
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input shift_en,
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input dir,
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input serial_in,
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input [N-1:0] parallel_in,
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output reg [N-1:0] q,
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output serial_out
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);
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assign serial_out = dir ? q[0] : q[N-1];
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always @(posedge clk or posedge rst) begin
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if (rst) q <= 0;
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else if (load) q <= parallel_in;
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else if (shift_en) begin
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if (dir == 0) q <= {q[N-2:0], serial_in};
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else q <= {serial_in, q[N-1:1]};
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end
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end
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endmodule |