34 lines
769 B
Verilog
34 lines
769 B
Verilog
`include "./adder_nbit/adder_nbit.v"
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module adder_nbit_tb;
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reg [7:0] a, b;
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reg carry_in;
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wire [7:0] sum;
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wire carry_out;
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adder_nbit adder_8bit(
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.a(a),
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.b(b),
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.carry_in(carry_in),
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.sum(sum),
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.carry_out(carry_out)
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);
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initial begin
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$dumpfile("./adder_nbit/adder_nbit.vcd");
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$dumpvars(0, adder_nbit_tb);
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a = 0; b = 5; carry_in = 0;
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#1
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$display("a=%d, b=%d, sum=%d, carry=%b", a, b, sum, carry_out);
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a = 10; b = 5; carry_in = 0;
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#1
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$display("a=%d, b=%d, sum=%d, carry=%b", a, b, sum, carry_out);
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a = 100; b = 5; carry_in = 0;
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#1
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$display("a=%d, b=%d, sum=%d, carry=%b", a, b, sum, carry_out);
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end
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endmodule |