48 lines
1.1 KiB
Verilog
48 lines
1.1 KiB
Verilog
/*
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fsm_traffic
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*/
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module fsm_traffic (
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input clk,
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input rst,
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output red_led,
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output green_led,
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output yellow_led
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);
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localparam RED = 2'b00;
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localparam GREEN = 2'b01;
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localparam YELLOW = 2'b10;
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reg[1:0] state, next_state;
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reg[7:0] timer;
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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state <= RED;
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timer <= 3;
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end
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else if (timer == 0) begin
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state <= next_state;
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case (next_state)
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RED: timer <= 3;
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YELLOW: timer <= 1;
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GREEN: timer <= 2;
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default: timer <= 3;
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endcase
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end
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else timer <= timer - 1;
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end
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always @(*) begin
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case (state)
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RED: next_state = GREEN;
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YELLOW: next_state = RED;
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GREEN: next_state = YELLOW;
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default: next_state = RED;
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endcase
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end
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assign red_led = state == RED;
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assign green_led = state == GREEN;
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assign yellow_led = state == YELLOW;
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endmodule |